The Semiconductor Value Chain: Fabless, Foundries, and IDMs

Introduction

The semiconductor industry is the foundation of the entire technology sector. Every device, data center, automobile, and industrial system depends on chips, and the companies that design, manufacture, and package these chips represent one of the most important coverage areas within TMT investment banking. The global semiconductor market reached approximately $740 billion in 2026, and the industry's strategic importance (for AI computing, national security, and economic competitiveness) has elevated chip companies from niche technology coverage to front-page deal flow. Understanding the semiconductor value chain, from chip design through fabrication, packaging, and testing, is essential for TMT analysts because each segment of the chain has different economics, different competitive dynamics, and different valuation frameworks.

The semiconductor industry is organized around three fundamental business models that determine how companies create and capture value.

Fabless: Design Without Manufacturing

Fabless Semiconductor Company

A chip company that designs integrated circuits but does not own or operate fabrication facilities (fabs). Fabless companies outsource manufacturing to foundries, allowing them to focus capital and engineering resources on chip design, architecture, and software. The fabless model dominates modern semiconductor economics because it avoids the massive capital investment required to build and maintain leading-edge fabs (a single advanced fab can cost $15-20 billion to construct). Nvidia, AMD, Qualcomm, Broadcom, Marvell, and MediaTek are the largest fabless semiconductor companies globally.

The fabless model has become the dominant approach for leading-edge chip design because it separates the capital-light, high-margin design function from the capital-intensive, lower-margin manufacturing function. Nvidia designs the world's most advanced AI accelerator chips (H100, B200, Blackwell) but does not manufacture a single one. Instead, Nvidia sends its designs to TSMC, which fabricates the chips in its advanced fabs in Taiwan, Japan, and Arizona. This separation allows Nvidia to operate at 60%+ gross margins and invest the majority of its revenue in R&D and software development, while TSMC operates at 50-55% gross margins and invests billions annually in new manufacturing capacity.

Fabless companies are valued primarily on their design intellectual property, their competitive positioning in specific end markets (AI, mobile, networking, automotive), and their revenue growth trajectory. The key financial metrics are gross margins (reflecting the premium the market pays for the chip design), R&D as a percentage of revenue (reflecting the investment in next-generation designs), and design win pipeline (reflecting future revenue from securing positions in customer products). Fabless companies in aggregate are growing revenue at a 6.96% CAGR through 2031, outpacing the broader semiconductor market, as the industry structurally shifts toward design-focused business models.

The fabless model's financial advantages are clear when comparing it to IDMs. A fabless company might generate 60-70% gross margins with 20-25% of revenue invested in R&D and minimal capex (5-8% of revenue), producing strong free cash flow. An IDM generating similar revenue might operate at 45-55% gross margins with 15-20% R&D spending and 20-30% capex, producing significantly lower free cash flow. This difference in capital efficiency is why fabless companies command higher valuation multiples: Nvidia trades at a premium to Intel despite both being semiconductor companies, because Nvidia's capital-light model generates superior returns on invested capital.

Foundries: Manufacturing as a Service

Foundries manufacture chips designed by other companies, operating factories that process silicon wafers through hundreds of steps to create finished integrated circuits. The foundry business model is capital-intensive (requiring billions in annual capex to maintain manufacturing leadership) but generates strong returns at scale because the fixed costs of running a fab are spread across dozens or hundreds of customers.

TSMC dominates the foundry market with approximately 66% market share in 2025, a position it has built over three decades by consistently delivering the most advanced manufacturing technology at the highest yields. Samsung Foundry holds approximately 11% market share, and the remaining share is split among GlobalFoundries, UMC, SMIC, and smaller players. The concentration of advanced manufacturing at TSMC is one of the most significant structural features of the global technology industry: virtually every AI chip, smartphone processor, and high-performance computing chip passes through TSMC's fabs.

Foundries are valued on capacity utilization (the percentage of available manufacturing capacity that is actually being used), technology leadership (which process nodes the foundry can offer), and capex intensity (the investment required to maintain competitiveness). A foundry operating at 80%+ utilization at leading-edge nodes generates strong margins (TSMC operates at 50-55% gross margins), while one at 60% utilization or focused on older nodes faces margin pressure. The foundry market reached $175.1 billion in 2025 and is projected to grow to $202 billion in 2026, driven primarily by AI chip demand that is consuming an increasing share of leading-edge capacity. TSMC's advanced packaging capacity (CoWoS) is expanding at 100% annually but still cannot fully meet demand from Nvidia and other AI chip designers, creating a bottleneck that constrains the pace of AI infrastructure deployment.

IDMs: Integrated Design and Manufacturing

Integrated device manufacturers (IDMs) both design and manufacture their own chips. Intel is the most prominent IDM, operating fabs in the US, Ireland, and Israel. Texas Instruments, Infineon, STMicroelectronics, and Samsung (for its own-brand chips) also operate as IDMs.

Integrated Device Manufacturer (IDM)

A semiconductor company that performs both chip design and chip manufacturing in-house, owning and operating its own fabrication facilities. The IDM model offers full control over the manufacturing process, enabling tight integration between design and production that can optimize performance and cost for specific chip architectures. However, the IDM model requires massive capital investment to maintain manufacturing competitiveness, and companies that fall behind on process technology face the difficult choice of continuing to invest billions in catching up or transitioning to a hybrid fabless-foundry model. IDMs commanded approximately 55% of total semiconductor industry revenue in 2025, though this share is gradually shifting toward fabless companies.

Intel's strategic transformation illustrates the complexity of the IDM model. Intel spent decades as the world's leading chipmaker but fell behind TSMC in manufacturing technology during the late 2010s, losing the process node leadership that had been central to its competitive advantage. Intel is now pursuing a dual strategy: continuing as an IDM for its own chip designs while building Intel Foundry Services (IFS) to compete with TSMC and Samsung as a contract manufacturer for other companies. This strategy requires sustained investment of $20+ billion annually in capex, a level of spending that pressures margins and free cash flow.

Samsung Foundry faces similar challenges: despite investing $44 billion in its Texas plant targeting 2nm production by 2026, yield issues at 3nm have cost it market share. The IDM model's fundamental challenge is that manufacturing competitiveness requires ever-increasing capital investment (each new process node costs more than the last to develop and deploy), and companies that fall behind face a widening gap that becomes progressively more expensive to close.

Texas Instruments represents a different IDM strategy. Rather than competing at the leading edge of process technology, TI focuses on analog and embedded processing chips manufactured on mature nodes (45nm and above). This approach avoids the escalating costs of leading-edge manufacturing while serving end markets (automotive, industrial) where chip performance is less dependent on transistor density and more dependent on reliability, power efficiency, and analog precision. TI's model generates consistent 60%+ gross margins and strong free cash flow, demonstrating that the IDM model remains viable when the company is not competing in the leading-edge manufacturing arms race.

Understanding the physical manufacturing process helps TMT analysts grasp why semiconductor economics differ so dramatically from software economics and why the value chain is structured the way it is.

The process begins with chip design (12-24 months), where engineers use EDA software to create a chip architecture, define the logic circuits, and produce a design layout that can be translated into manufacturing instructions. This design phase is the fabless company's core activity and represents the intellectual property that commands premium valuations.

The design is then sent to a foundry for fabrication (3-4 months per wafer lot). Fabrication involves processing silicon wafers through hundreds of sequential steps: lithography (using light to pattern circuit features onto the wafer), etching (removing material to create the patterned structures), deposition (adding layers of conducting and insulating materials), and ion implantation (modifying the electrical properties of specific regions). A leading-edge fab runs 24/7 and processes each wafer through 1,000+ individual steps over approximately 3 months. The wafer emerges containing hundreds of individual chip "dies."

After fabrication, wafers go to assembly and packaging (OSAT companies or in-house packaging), where individual dies are cut from the wafer, mounted on substrates, connected to external pins, and encapsulated in protective packaging. Advanced packaging (chiplets, 3D stacking, TSMC's CoWoS) has become a critical performance differentiator for AI chips, where connecting multiple dies together in a single package enables higher performance than any single die could achieve.

Finally, testing verifies that each chip functions correctly and meets performance specifications. Chips that fail testing are discarded, and the percentage that pass (the "yield") is a critical metric for manufacturing economics. A foundry achieving 80% yield on a new process node is producing 20% fewer usable chips than the wafer capacity would suggest, directly impacting per-chip cost and profitability.

The total time from design start to finished, tested chip is typically 18-36 months, which creates long planning cycles and makes the semiconductor industry uniquely sensitive to demand forecasting errors, a key dynamic that drives the semiconductor business cycle and creates significant analytical complexity.

Beyond the core design-foundry-IDM triangle, the semiconductor value chain includes several other critical segments that generate M&A activity and advisory mandates.

Electronic Design Automation (EDA) companies (Synopsys, Cadence Design Systems, Siemens EDA) provide the software tools that chip designers use to create integrated circuit layouts. EDA is a duopoly dominated by Synopsys and Cadence, which together hold over 60% of the market. The EDA segment operates with SaaS-like economics (high recurring revenue, strong retention, 85%+ gross margins) and is valued on software multiples rather than semiconductor multiples. Synopsys's $35 billion acquisition of Ansys in 2024 demonstrated the scale of M&A in the EDA space.

Semiconductor IP companies (Arm Holdings, Imagination Technologies, CEVA) license reusable chip design blocks (processor cores, interfaces, security modules) that other companies incorporate into their own chips. Arm's processor architecture powers virtually every smartphone on the planet and is increasingly used in data center and automotive applications. Arm's business model (licensing IP for upfront fees and per-unit royalties) generates high margins and recurring revenue that is leveraged to the total volume of chips shipped globally. With a market capitalization exceeding $150 billion following its 2023 re-IPO, Arm demonstrates how IP-centric semiconductor businesses can command premium valuations by capturing value from the entire ecosystem rather than competing within a single segment.

Outsourced Semiconductor Assembly and Test (OSAT) companies (ASE Technology, Amkor Technology) handle the back-end of the manufacturing process: packaging finished wafers into usable chips and testing them for quality. OSAT is growing in strategic importance as advanced packaging technologies (TSMC's CoWoS, chiplet architectures) become critical for AI chip performance. TSMC's CoWoS capacity is expanding from 330,000 wafers in 2024 to 660,000 in 2025, a 100% annual increase driven by demand for AI accelerator packaging.

The semiconductor value chain generates M&A and capital markets activity across every segment. Fabless companies acquire to expand their product portfolios and enter new end markets: Broadcom's serial acquisition strategy has built a $700+ billion market cap company through deals like the $61 billion VMware acquisition and the $69 billion Qualcomm bid (ultimately withdrawn). AMD's $49 billion acquisition of Xilinx expanded its portfolio into FPGAs and adaptive computing. Foundries invest in capacity expansion that generates construction, equipment procurement, and financing advisory work. IDMs explore strategic alternatives as the cost of maintaining manufacturing competitiveness escalates. EDA companies consolidate to create integrated design platforms. OSAT companies are being acquired as advanced packaging becomes a competitive differentiator.

For TMT analysts, the semiconductor value chain requires understanding both the financial metrics specific to each segment (utilization rates for foundries, design win pipeline for fabless, wafer starts for IDMs) and the interconnections between segments. A surge in AI chip demand benefits fabless designers (Nvidia), their foundry partner (TSMC), the equipment makers that supply the fabs (ASML, Applied Materials), the packaging companies that assemble the chips (ASE), and the EDA companies whose tools are used to design them (Synopsys, Cadence). Modeling these interconnections is what makes semiconductor analysis uniquely complex and rewarding within TMT coverage.

The geopolitical dimension of semiconductor M&A adds a layer of complexity that does not exist in software or internet transactions. Export controls (particularly US restrictions on advanced chip technology to China), foreign investment restrictions (CFIUS in the US, similar regimes in Europe and Asia), and government subsidy programs all influence deal feasibility, structuring, and timeline. TMT bankers advising on semiconductor transactions must carefully navigate these regulatory considerations alongside traditional financial and strategic analysis.